Figure 186. Counter Timing Diagram, Internal Clock Divided By 4; Figure 187. Counter Timing Diagram, Internal Clock Divided By N; Preloaded) - STMicroelectronics STM32F405 Reference Manual

RM0090
Figure 188. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not

Figure 186. Counter timing diagram, internal clock divided by 4

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 187. Counter timing diagram, internal clock divided by N

CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
DocID018909 Rev 11
General-purpose timers (TIM9 to TIM14)
0035
1F
20

preloaded)

CEN
31 32 33 34 35 36
FF
0036 0000 0001
00
00 01 02 03 04 05 06 07
36
647/1731
687