Reload Register (Iwdg_Rlr) - STMicroelectronics STM32F405 Reference Manual

Independent watchdog (IWDG)
21.4.3

Reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:12 Reserved, must be kept at reset value.
Bits11:0 RL[11:0]: Watchdog counter reload value
Note: Reading this register returns the reload value from the VDD voltage domain. This value
21.4.4 Status register (IWDG_SR)
Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 RVU: Watchdog counter reload value update
Bit 0 PVU: Watchdog prescaler value update
Note: If several reload values or prescaler values are used by application, it is mandatory to wait
until RVU bit is reset before changing the reload value and to wait until PVU bit is reset
before changing the prescaler value. However, after updating the prescaler and/or the
reload value it is not necessary to wait until RVU or PVU is reset before continuing code
execution (even in case of low-power mode entry, the write operation is taken into account
and will complete)
702/1731
Reserved
These bits are write access protected see
define the value to be loaded in the watchdog counter each time the value AAAAh is written
in the IWDG_KR register. The watchdog counter counts down from this value. The timeout
period is a function of this value and the clock prescaler. Refer to
The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload
value.
may not be up to date/valid if a write operation to this register is ongoing on this
register. For this reason the value read from this register is valid only when the RVU bit
in the IWDG_SR register is reset.
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the V
(takes up to 5 RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the V
domain (takes up to 5 RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.
DocID018909 Rev 11
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Section
Reserved
9 8 7 6 5
RL[11:0]
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21.3.2. They are written by software to
Table 106.
9 8 7 6 5 4
DD
RM0090
4 3 2 1 0
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3 2 1 0
RVU PVU
r r
voltage domain
voltage
DD