Figure 269. Example; Figure 270. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length With Cpol = 0 - STMicroelectronics STM32F405 Reference Manual

Serial peripheral interface (SPI)
For transmission, each time an MSB is written to SPI_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load SPI_DR with the new value to send. This takes
place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.

Figure 270. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0

CK
WS
SD
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).
896/1731

Figure 269. Example

Only one access to SPI_DR
Transmission
Reception
May be 16-bit, 32-bit
MSB
Channel left
DocID018909 Rev 11
0X76A3
LSB MSB
RM0090
Channel right