Table 300. Sw-Dp Registers; Dp And Ap Read/Write Accesses - STMicroelectronics STM32F405 Reference Manual

Debug support (DBG)
Further details of the SW-DP state machine can be found in the Cortex
TRM and the CoreSight Design Kit r0p1 TRM.
38.8.4

DP and AP read/write accesses

•
Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
•
Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
•
The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is "WAIT". With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
•
Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.
38.8.5 SW-DP registers
Access to these registers are initiated when APnDP=0
A[3:2]
00 Read
00 Write
01 Read/Write
01 Read/Write
10 Read
1682/1731

Table 300. SW-DP registers

CTRLSEL bit
R/W of SELECT
register
-
-
0
1
-
DocID018909 Rev 11
Register
The manufacturer code is not set to ST
IDCODE
code. 0x2BA01477 (identifies the SW-DP)
ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
DP- accesses
CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-
up acknowledges)
Purpose is to configure the physical serial
WIRE
port protocol (like the duration of the
CONTROL
turnaround time)
Enables recovery of the read data from a
READ
corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
RM0090
®
-M4 with FPU r0p1
Notes
-