Figure 101. Counter Timing Diagram, Internal Clock Divided By 2; Figure 102. Counter Timing Diagram, Internal Clock Divided By 4, Timx_Arr=0X36; Figure 103. Counter Timing Diagram, Internal Clock Divided By N - STMicroelectronics STM32F405 Reference Manual

RM0090

Figure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

1.
Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 101. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
CK_PSC
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 103. Counter timing diagram, internal clock divided by N

CK_PSC
Timer clock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
DocID018909 Rev 11
Advanced-control timers (TIM1&TIM8)
0003 0002 0001 0000 0001 0002 0003
0034 0035
20 1F 01
0036 0035
00
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