Rcc Ahb1 Peripheral Reset Register (Rcc_Ahb1Rstr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bit 3 HSERDYF: HSE ready interrupt flag
Bit 2 HSIRDYF: HSI ready interrupt flag
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
6.3.5

RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31 30 29 28
OTGH
S
Reserved
RST
rw
15 14 13 12
CRCR
ST
Reserved
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 OTGHSRST: USB OTG HS module reset
Bits 28:26 Reserved, must be kept at reset value.
170/1731
This bit is set by hardware when External High Speed clock becomes stable and
HSERDYDIE is set.
It is cleared by software by setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
This bit is set by hardware when the Internal High Speed clock becomes stable and
HSIRDYDIE is set.
It is cleared by software by setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
This bit is set by hardware when the External Low Speed clock becomes stable and
LSERDYDIE is set.
It is cleared by software by setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
This bit is set by hardware when the internal low speed clock becomes stable and
LSIRDYDIE is set.
It is cleared by software by setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
27 26 25
ETHMAC
RST
Reserved
rw
11 10 9
GPIOK GPIOJ
RST RST
Res.
rw rw
This bit is set and cleared by software.
0: does not reset the USB OTG HS module
1: resets the USB OTG HS module
DocID018909 Rev 11
24 23 22
DMA2D DMA2 DMA1
RST RST
Res.
rw rw
8 7 6
GPIOI GPIOH GPIOGG GPIOF
RST RST RST
rw rw rw
21 20 19 18
RST
Reserved
rw
5 4 3 2
GPIOE GPIOD GPIOC
RST RST RST RST
rw rw rw rw
RM0090
17 16
1 0
GPIOB GPIOA
RST RST
rw rw