Rcc Spread Spectrum Clock Generation Register (Rcc_Sscgr) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
6.3.22

RCC spread spectrum clock generation register (RCC_SSCGR)

Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after
the main PLL disabled.
Note: For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the "Electrical characteristics" section in your device datasheet.
31 30 29
SPR
SSCG
EAD
EN
Reserved
SEL
rw rw
15 14 13
INCSTEP
rw rw rw
Bit 31 SSCGEN: Spread spectrum modulation enable
Bit 30 SPREADSEL: Spread Select
202/1731
This bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is
stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
0: LSI RC oscillator not ready
1: LSI RC oscillator ready
This bit is set and cleared by software.
0: LSI RC oscillator OFF
1: LSI RC oscillator ON
28 27 26 25
rw rw rw
12 11 10 9
rw rw rw rw
This bit is set and cleared by software.
0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
This bit is set and cleared by software.
To write before to set CR[24]=PLLON bit.
0: Center spread
1: Down spread
DocID018909 Rev 11
24 23 22 21
INCSTEP
rw rw rw
8 7 6 5
MODPER
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2 1
rw rw rw rw
RM0090
16
rw
0
rw