Digital camera interface (DCMI)
8-bit data
When EDM[1:0] in DCMI_CR are programmed to "00" the interface captures 8 LSB's at its
input (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to
capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4
captured data byte is placed in the MSB position in the 32-bit word.
example of the positioning of captured data bytes in two 32-bit words.
Table 79. Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address
0
4
10-bit data
When EDM[1:0] in DCMI_CR are programmed to "01", the camera interface captures 10-bit
data at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The
remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero.
So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in
Table 80. Positioning of captured data bytes in 32-bit words (10-bit width)
Byte address
0
4
12-bit data
When EDM[1:0] in DCMI_CR are programmed to "10", the camera interface captures the
12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2
captured data are placed in the MSB position in the 32-bit word as shown in
Table 81. Positioning of captured data bytes in 32-bit words (12-bit width)
Byte address
0
4
14-bit data
When EDM[1:0] in DCMI_CR are programmed to "11", the camera interface captures the
14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit
460/1731
31:24
23:16
D
[7:0]
D
n+3
n+2
D
[7:0]
D
n+7
n+6
31:26
25:16
0
D
n+1
0
D
n+3
31:28
27:16
0
D
n+1
0
D
n+3
DocID018909 Rev 11
15:8
[7:0]
D
[7:0]
n+1
[7:0]
D
[7:0]
n+5
15:10
[9:0]
0
[9:0]
0
15:12
[11:0]
0
[11:0]
0
RM0090
th
Table 79
gives an
7:0
D
[7:0]
n
D
[7:0]
n+4
nd
Table
80.
9:0
D
[9:0]
n
D
[9:0]
n+2
nd
Table
81.
11:0
D
[11:0]
n
D
[11:0]
n+2
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