Rcc Clock Interrupt Register (Rcc_Cir) - STMicroelectronics STM32F405 Reference Manual

Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC)
Bits 7:4 HPRE: AHB prescaler
Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
Bits 3:2 SWS: System clock switch status
Bits 1:0 SW: System clock switch
7.3.4

RCC clock interrupt register (RCC_CIR)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
15 14 13
PLLI2S
RDYIE RDYIE
Reserved
rw
230/1731
Set and cleared by software to control AHB clock division factor.
HPRE write.
0xxx: system clock not divided
1000: system clock divided by 2
1001: system clock divided by 4
1010: system clock divided by 8
1011: system clock divided by 16
1100: system clock divided by 64
1101: system clock divided by 128
1110: system clock divided by 256
1111: system clock divided by 512
Set and cleared by hardware to indicate which clock source is used as the system clock.
00: HSI oscillator used as the system clock
01: HSE oscillator used as the system clock
10: PLL used as the system clock
11: not applicable
Set and cleared by software to select the system clock source.
Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in
case of failure of the HSE oscillator used directly or indirectly as the system clock.
00: HSI oscillator selected as system clock
01: HSE oscillator selected as system clock
10: PLL selected as system clock
11: not allowed
28 27 26 25
Reserved
12 11 10 9
PLL HSE HSI LSE
RDYIE RDYIE RDYIE
rw rw rw rw
DocID018909 Rev 11
24 23 22 21
PLLI2S
CSSC
Reserv
RDYC
ed
w
8 7 6
LSI PLLI2S
CSSF
Reserv
RDYIE RDYF
ed
rw r
20 19 18
PLL HSE HSI
RDYC RDYC RDYC
w w w w
5 4 3 2
PLL HSE HSI
RDYF RDYF RDYF
r r r r
RM0090
17 16
LSE LSI
RDYC RDYC
w w
1 0
LSE LSI
RDYF RDYF
r r