Table 259. Non-Multiplexed I/O Nor Flash Memory; Table 260. 16-Bit Multiplexed I/O Nor Flash Memory; Table 261. Non-Multiplexed I/Os Psram/Sram - STMicroelectronics STM32F405 Reference Manual

RM0090
NOR Flash memory, non-multiplexed I/Os
The maximum capacity is 512 Mbits (26 address lines).
NOR Flash memory, 16-bit multiplexed I/Os
FMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT
The maximum capacity is 512 Mbits.
PSRAM/SRAM, non-multiplexed I/Os
FMC signal name
CLK
A[25:0]
D[31:0]

Table 259. Non-multiplexed I/O NOR Flash memory

FMC signal name
CLK
A[25:0]
D[31:0]
NE[x]
NOE
NWE
NL(=NADV)
NWAIT

Table 260. 16-bit multiplexed I/O NOR Flash memory

I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
O
O
O
Latch enable (this signal is called address valid, NADV, by some NOR
O
I

Table 261. Non-multiplexed I/Os PSRAM/SRAM

I/O
O
O
I/O
DocID018909 Rev 11
I/O
O
O
I/O
O
O
O
Latch enable (this signal is called address
O
valid, NADV, by some NOR Flash devices)
I NOR Flash wait input signal to the FMC
Function
Clock (for synchronous access)
Address bus
A[15:0] and data D[15:0] are multiplexed on the databus)
Chip Select, x = 1..4
Output enable
Write enable
Flash devices)
NOR Flash wait input signal to the FMC
Function
Clock (only for PSRAM synchronous access)
Address bus
Data bidirectional bus
Flexible memory controller (FMC)
Function
Clock (for synchronous access)
Address bus
Bidirectional data bus
Chip Select, x = 1..4
Output enable
Write enable
1601/1731
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