Software Interrupt Event Register (Exti_Swier) - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus
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Interrupts and events
12.3.5

Software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
15
14
13
SWIER
SWIER
SWIER
SWIER
15
14
13
rw
rw
rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 SWIERx: Software Interrupt on line x
12.3.6
Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31
30
29
15
14
13
PR15
PR14
PR13
PR12
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 PRx: Pending bit
388/1731
28
27
26
25
Reserved
12
11
10
9
SWIER
SWIER
SWIER
12
11
10
9
rw
rw
rw
rw
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
28
27
26
25
Reserved
12
11
10
9
PR11
PR10
PR9
rc_w1
rc_w1
rc_w1
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to '1'.
DocID018909 Rev 11
24
23
22
21
SWIER
SWIER
22
21
rw
rw
8
7
6
SWIER
SWIER
SWIER
SWIER
8
7
6
rw
rw
rw
rw
24
23
22
21
PR22
PR21
rc_w1
rc_w1
8
7
6
PR8
PR7
PR6
PR5
rc_w1
rc_w1
rc_w1
rc_w1
20
19
18
SWIER
SWIER
SWIER
20
19
18
rw
rw
rw
5
4
3
2
SWIER
SWIER
SWIER
5
4
3
2
rw
rw
rw
20
19
18
PR20
PR19
PR18
rc_w1
rc_w1
rc_w1
5
4
3
2
PR4
PR3
PR2
rc_w1
rc_w1
rc_w1
RM0090
17
16
SWIER
SWIER
17
16
rw
rw
1
0
SWIER
SWIER
1
0
rw
rw
17
16
PR17
PR16
rc_w1
rc_w1
1
0
PR1
PR0
rc_w1
rc_w1

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