Figure 54. Regular Simultaneous Mode On 16 Channels: Dual Adc Mode; Figure 55. Regular Simultaneous Mode On 16 Channels: Triple Adc Mode - STMicroelectronics STM32F405 Reference Manual

RM0090
Dual ADC mode
At the end of conversion event on ADC1 or ADC2:
•
A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register
are equal to 0b10). This request transfers the ADC2 converted data stored in the upper
half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted
data stored in the lower half-word of ADC_CCR to the SRAM.
•
An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2's regular channels have all been converted.

Figure 54. Regular simultaneous mode on 16 channels: dual ADC mode

Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
•
Three 32-bit DMA transfer requests are generated (if DMA[1:0] bits in the ADC_CCR
register are equal to 0b01). Three transfers then take place from the ADC_CDR 32-bit
register to SRAM: first the ADC1 converted data, then the ADC2 converted data and
finally the ADC3 converted data. The process is repeated for each new three
conversions.
•
An EOC interrupt is generated (if enabled on one of the three ADC interfaces) when the
ADC1/ADC2/ADC3's regular channels are have all been converted.

Figure 55. Regular simultaneous mode on 16 channels: triple ADC mode

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