Stop Mode (Stm32F405Xx/07Xx And Stm32F415Xx/17Xx); Table 25. Sleep-On-Exit Entry And Exit - STMicroelectronics STM32F405 Reference Manual

Power controller (PWR)
Sleep-now mode
Mode exit
Wakeup latency
Sleep-on-exit
Mode entry
Mode exit
Wakeup latency
5.3.4

Stop mode (STM32F405xx/07xx and STM32F415xx/17xx)

The Stop mode is based on the Cortex
peripheral clock gating. The voltage regulator can be configured either in normal or low-
power mode. In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI
and the HSE RC oscillators are disabled. Internal SRAM and register contents are
preserved.
By setting the FPDS bit in the PWR_CR register, the Flash memory also enters power-down
mode when the device enters Stop mode. When the Flash memory is in power-down mode,
an additional startup delay is incurred when waking up from Stop mode (see
operating modes (STM32F405xx/07xx and STM32F415xx/17xx)
power control register (PWR_CR) for STM32F405xx/07xx and
130/1731
Table 24. Sleep-now entry and exit (continued)
If WFI or Return from ISR was used for entry:
Interrupt: Refer to Table 61: Vector table for STM32F405xx/07xx and
STM32F415xx/17xx
STM32F43xxx
If WFE was used for entry and SEVONPEND = 0
Wakeup event: Refer to
f WFE was used for entry and SEVONPEND = 1
Interrupt even when disabled in NVIC: refer to
STM32F405xx/07xx and STM32F415xx/17xx
for STM32F42xxx and STM32F43xxx
Section 12.2.3: Wakeup event
None

Table 25. Sleep-on-exit entry and exit

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0, and
– No interrupt (for WFI) or event (for WFE) is pending.
®
Refer to the Cortex -M4 with FPU System Control register.
On Return from ISR while:
– SLEEPDEEP = 0, and
– SLEEPONEXIT = 1, and
– No interrupt is pending.
®
Refer to the Cortex -M4 with FPU System Control register.
Interrupt: refer to Table 61: Vector table for STM32F405xx/07xx and
STM32F415xx/17xx
STM32F43xxx
None
®
-M4 with FPU deepsleep mode combined with
DocID018909 Rev 11
Description
and Table 62: Vector table for STM32F42xxx and
Section 12.2.3: Wakeup event management
or Wakeup event (see
management).
Description
and Table 62: Vector table for STM32F42xxx and
STM32F415xx/17xx).
RM0090
Table 61: Vector table for
and Table 62: Vector table
Table 26: Stop
and Section 5.4.1: PWR