Table 206. Data Fifo (Dfifo) Access Register Map; Table 207. Power And Clock Gating Control And Status Registers; Otg_Hs Global Registers - STMicroelectronics STM32F405 Reference Manual

RM0090
Data FIFO (DFIFO) access register map
These registers, available in both host and peripheral modes, are used to read or write the
FIFO space for a specific endpoint or a channel, in a given direction. If a host channel is of
type IN, the FIFO can only be read on the channel. Similarly, if a host channel is of type
OUT, the FIFO can only be written on the channel.
Device IN Endpoint 0/Host OUT Channel 0: DFIFO Write Access
Device OUT Endpoint 0/Host IN Channel 0: DFIFO Read Access
Device IN Endpoint 1/Host OUT Channel 1: DFIFO Write Access
Device OUT Endpoint 1/Host IN Channel 1: DFIFO Read Access
...
Device IN Endpoint x
Device OUT Endpoint x
1. Where x is 5 in peripheral mode and 11 in host mode.
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and
peripheral modes.
Power and clock gating control register
Reserved
35.12.2

OTG_HS global registers

These registers are available in both host and peripheral modes, and do not need to be
reprogrammed when switching between these modes.
Bit values in the register descriptions are expressed in binary unless otherwise specified.
OTG_HS control and status register (OTG_HS_GOTGCTL)
Address offset: 0x000
Reset value: 0x0000 0800
The OTG control and status register controls the behavior and reflects the status of the OTG
function of the core.

Table 206. Data FIFO (DFIFO) access register map

FIFO access register section
(1)
/Host OUT Channel x
(1)
/Host IN Channel x

Table 207. Power and clock gating control and status registers

Register name
DocID018909 Rev 11
USB on-the-go high-speed (OTG_HS)
(1)
: DFIFO Write Access
(1)
: DFIFO Read Access
Acronym Offset address: 0xE00–0xFFF
PCGCR 0xE00-0xE04
0xE05–0xFFF
Address range Access
w
0x1000–0x1FFC
r
w
0x2000–0x2FFC
r
... ...
w
0xX000h–0xXFFC
r
1393/1731
1529