Rcc Ahb3 Peripheral Clock Enable In Low Power Mode Register (Rcc_Ahb3Lpenr); Rcc Apb1 Peripheral Clock Enable In Low Power Mode Register (Rcc_Apb1Lpenr) - STMicroelectronics STM32F405 Reference Manual

RM0090
6.3.17 RCC AHB3 peripheral clock enable in low power mode register
(RCC_AHB3LPENR)
Address offset: 0x58
Reset value: 0x0000 0001
Access: no wait state, word, half-word and byte access.
31 30 29
15 14 13
Bits 31:1Reserved, must be kept at reset value.
FMCLPEN: Flexible memory controller module clock enable during Sleep mode
Bit 0
6.3.18 RCC APB1 peripheral clock enable in low power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xF6FE C9FF
Access: no wait state, word, half-word and byte access.
31 30 29
UART8 UART7 DAC PWR
LPEN LPEN LPEN LPEN
rw rw rw
15 14 13
SPI3 SPI2
LPEN LPEN
Reserved
rw rw
Reset and clock control for STM32F42xxx and STM32F43xxx (RCC)
28 27 26 25
12 11 10 9
This bit is set and cleared by software.
0: FMC module clock disabled during Sleep mode
1: FMC module clock enabled during Sleep mode
28 27 26 25
CAN2 CAN1
RESER
VED
LPEN LPEN
rw rw rw
12 11 10 9
WWDG
LPEN
Reserved
rw
DocID018909 Rev 11
24 23 22
Reserved
8 7 6
Reserved
24 23 22 21
I2C3 I2C2 I2C1
Reser-
LPEN LPEN LPEN
ved
rw rw
8 7 6
TIM14 TIM13 TIM12 TIM7
LPEN LPEN LPEN LPEN
rw rw rw
21 20 19 18
5 4 3 2
20 19 18
USART
UART5 UART4
3
LPEN LPEN
LPEN
rw rw rw rw
5 4 3 2
TIM6 TIM5 TIM4
LPEN LPEN LPEN
rw rw rw rw
17 16
1 0
FMC
LPEN
rw
17 16
USART
2
Reser-
LPEN
ved
rw
1 0
TIM3 TIM2
LPEN LPEN
rw rw
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