Sdio Interrupt Clear Register (Sdio_Icr) - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus
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RM0090
Bit 4 TXUNDERR: Transmit FIFO underrun error
Bit 3 DTIMEOUT: Data timeout
Bit 2 CTIMEOUT: Command response timeout
Bit 1 DCRCFAIL: Data block sent/received (CRC check failed)
Bit 0 CCRCFAIL: Command response received (CRC check failed)
31.9.12

SDIO interrupt clear register (SDIO_ICR)

Address offset: 0x38
Reset value: 0x0000 0000
The SDIO_ICR register is a write-only register. Writing a bit with 1b clears the corresponding
bit in the SDIO_STA Status register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
Bits 31:24 Reserved, must be kept at reset value
Bit 23 CEATAENDC: CEATAEND flag clear bit
Bit 22 SDIOITC: SDIOIT flag clear bit
Bits 21:11 Reserved, must be kept at reset value
Bit 10 DBCKENDC: DBCKEND flag clear bit
Bit 9 STBITERRC: STBITERR flag clear bit
Bit 8 DATAENDC: DATAEND flag clear bit
The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.
rw rw
Set by software to clear the CEATAEND flag.
0: CEATAEND not cleared
1: CEATAEND cleared
Set by software to clear the SDIOIT flag.
0: SDIOIT not cleared
1: SDIOIT cleared
Set by software to clear the DBCKEND flag.
0: DBCKEND not cleared
1: DBCKEND cleared
Set by software to clear the STBITERR flag.
0: STBITERR not cleared
1: STBITERR cleared
Set by software to clear the DATAEND flag.
0: DATAEND not cleared
1: DATAEND cleared
DocID018909 Rev 11
Secure digital input/output interface (SDIO)
Reserved
9
8
7
6
5
4
rw rw rw rw rw rw rw rw rw rw rw
3
2
1
0
1061/1731
1067

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