Host-Mode Registers - STMicroelectronics STM32F405 Reference Manual

USB on-the-go high-speed (OTG_HS)
Bits 31:16 INEPTXFD: IN endpoint TxFIFO depth
Bits 15:0 INEPTXSA: IN endpoint FIFOx transmit RAM start address
35.12.3

Host-mode registers

Bit values in the register descriptions are expressed in binary unless otherwise specified.
Host-mode registers affect the operation of the core in the host mode. Host mode registers
must not be accessed in peripheral mode, as the results are undefined. Host mode registers
can be categorized as follows:
OTG_HS host configuration register (OTG_HS_HCFG)
Address offset: 0x400
Reset value: 0x0000 0000
This register configures the core after power-on. Do not change to this register after
initializing the host.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bits 31:3 Reserved, must be kept at reset value.
Bit 2 FSLSS: FS- and LS-only support
Bits 1:0 FSLSPCS: FS/LS PHY clock select
Note: The FSLSPCS bit must be set on a connection event according to the speed of the
1418/1731
This value is in terms of 32-bit words.
Minimum value is 16
Maximum value is 512
The power-on reset value of this register is specified as the largest IN endpoint FIFO
number depth.
This field contains the memory start address for IN endpoint transmit FIFOx. The address
must be aligned with a 32-bit memory location.
The application uses this bit to control the core's enumeration speed. Using this bit, the
application can make the core enumerate as an FS host, even if the connected device
supports HS traffic. Do not make changes to this field after initial programming.
0: HS/FS/LS, based on the maximum speed supported by the connected device
1: FS/LS-only, even if the connected device can support HS (read-only)
When the core is in FS host mode:
01: PHY clock is running at 48 MHz
Others: Reserved
When the core is in LS host mode:
00: Reserved
01: PHY clock is running at 48 MHz.
10: Select 6 MHz PHY clock frequency
11: Reserved
connected device. A software reset must be performed after changing this bit.
DocID018909 Rev 11
9 8 7 6 5 4 3
RM0090
2 1 0
r rw rw