Table 101. Output Control Bit For Standard Ocx Channels; Tim9/12 Counter (Timx_Cnt) - STMicroelectronics STM32F405 Reference Manual

RM0090
CCxE bit
0
1
Note: The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.
19.4.8

TIM9/12 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13
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Bits 15:0 CNT[15:0]: Counter value
19.4.9 TIM9/12 prescaler (TIMx_PSC)
Address offset: 0x28
Reset value: 0x0000
15 14 13
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Bits 15:0 PSC[15:0]: Prescaler value
19.4.10 TIM9/12 auto-reload register (TIMx_ARR)
Address offset: 0x2C
Reset value: 0x0000
15 14 13
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Bits 15:0 ARR[15:0]: Auto-reload value

Table 101. Output control bit for standard OCx channels

Output disabled (OCx='0', OCx_EN='0')
OCx=OCxREF + Polarity, OCx_EN='1'
12 11 10 9
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12 11 10 9
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The counter clock frequency CK_CNT is equal to f
PSC contains the value to be loaded into the active prescaler register at each update event.
12 11 10 9
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ARR is the value to be loaded into the actual auto-reload register.
Refer to the Section 19.3.1: Time-base unit on page 644
and behavior.
The counter is blocked while the auto-reload value is null.
DocID018909 Rev 11
General-purpose timers (TIM9 to TIM14)
OCx output state
8 7 6 5
CNT[15:0]
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8 7 6 5
PSC[15:0]
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CK_PSC
8 7 6 5
ARR[15:0]
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4 3 2
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4 3 2
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/ (PSC[15:0] + 1).
4 3 2
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for more details about ARR update
1 0
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1 0
rw
1 0
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