Table 262. 16-Bit Multiplexed I/O Psram; Supported Memories And Transactions - STMicroelectronics STM32F405 Reference Manual

Flexible memory controller (FMC)
FMC signal name
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[3]
NBL[2]
NBL[1]
NBL[0]
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
FMC signal name
CLK
A[25:16]
AD[15:0]
NE[x]
NOE
NWE
NL(= NADV)
NWAIT
NBL[1]
NBL[0]
The maximum capacity is 512 Mbits (26 address lines).
37.5.2

Supported memories and transactions

Table 263
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
1602/1731
Table 261. Non-multiplexed I/Os PSRAM/SRAM (continued)
I/O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e.
O
O
O
O Address valid only for PSRAM input (memory signal name: NADV)
I
O
O
O
O
Table 262.
I/O
O
O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
I/O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e.
O
O
O
O
I
O
O
below shows an example of the supported devices, access modes and
DocID018909 Rev 11
Output enable
Write enable
PSRAM wait input signal to the FMC
Byte3 Upper byte enable (memory signal name: NUB)
Byte2 Lowed byte enable (memory signal name: NLB)
Byte1 Upper byte enable (memory signal name: NLB)
Byte0 Lower byte enable (memory signal name: NLB)
16-Bit
multiplexed I/O PSRAM
Clock (for synchronous access)
Address bus
A[15:0] and data D[15:0] are multiplexed on the databus)
Output enable
Write enable
Address valid PSRAM input (memory signal name: NADV)
PSRAM wait input signal to the FMC
Upper byte enable (memory signal name: NUB)
Lowed byte enable (memory signal name: NLB)
Function
CRAM))
Function
CRAM))
RM0090