Table 71. Adc Global Register Map; Table 72. Adc Register Map And Reset Values For Each Adc - STMicroelectronics STM32F405 Reference Manual

Analog-to-digital converter (ADC)
13.13.17 ADC common regular data register for dual and triple modes
(ADC_CDR)
Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions
– In dual mode, these bits contain the regular data of ADC2. Refer to
– In triple mode, these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
Bits 15:0 DATA1[15:0]: 1st data item of a pair of regular conversions
– In dual mode, these bits contain the regular data of ADC1. Refer to
– In triple mode, these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
13.13.18 ADC register map
The following table summarizes the ADC registers.
Offset
0x000 - 0x04C
0x050 - 0x0FC
0x100 - 0x14C
0x118 - 0x1FC
0x200 - 0x24C
0x250 - 0x2FC
0x300 - 0x308

Table 72. ADC register map and reset values for each ADC

Offset Register
ADC_SR
0x00
Reset value
432/1731
27 26 25
r r r r
11 10 9
r r r r
Refer to Triple ADC mode.
Refer to Triple ADC mode.

Table 71. ADC global register map

DocID018909 Rev 11
24 23 22 21
DATA2[15:0]
r r r r
8 7 6 5
DATA1[15:0]
r r r r
Register
ADC1
Reserved
ADC2
Reserved
ADC3
Reserved
Common registers
Reserved
20 19 18 17
r r r r
4 3 2 1
r r r r
Dual ADC mode.
Dual ADC mode
0 0 0
RM0090
16
r
0
r
0 0 0