Figure 348. Event Flags And Interrupt Generation - STMicroelectronics STM32F405 Reference Manual

RM0090
CAN_TSR
CAN_RF0R
CAN_RF1R
CAN_ESR
CAN_MSR
•
The transmit interrupt can be generated by the following events:
–
–
–
• The FIFO 0 interrupt can be generated by the following events:
–
–
–
• The FIFO 1 interrupt can be generated by the following events:
–
–
–
• The error and status change interrupt can be generated by the following events:
–

Figure 348. Event flags and interrupt generation

CAN_IER
TMEIE
RQCP0
+
RQCP1
RQCP2
FMPIE0
FMP0
FFIE0
FULL0
FOVIE0
FOVR0
FMPIE1
FMP1
FFIE1
FULL1
FOVIE1
FOVR1
ERRIE
EWGIE
EWGF
EPVIE
EPVF
BOFIE
BOFF
LECIE
1≤LEC≤6
WKUIE
WKUI
SLKIE
SLAKI
Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.
Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.
Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.
Reception of a new message, FMP0 bits in the CAN_RF0R register are not '00'.
FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.
FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.
Reception of a new message, FMP1 bits in the CAN_RF1R register are not '00'.
FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.
Error condition, for more details on error conditions please refer to the CAN Error
Status register (CAN_ESR).
DocID018909 Rev 11
Controller area network (bxCAN)
TRANSMIT
INTERRUPT
&
&
FIFO 0
INTERRUPT
+
&
&
&
FIFO 1
INTERRUPT
& +
&
&
&
+
ERRI
&
CAN_MSR
&
&
STATUS CHANGE
ERROR
INTERRUPT
+
&
&
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