Table 35. Port Bit Configuration Table; Figure 25. Basic Structure Of A Five-Volt Tolerant I/O Port Bit - STMicroelectronics STM32F405 Reference Manual

General-purpose I/Os (GPIO)
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no
risk of an IRQ occurring between the read and the modify access.
Figure 25
port bit configurations.
1. V
DD_FT
MODER(i)
[1:0]
01
270/1731
shows the basic structure of a 5 V tolerant I/O port bit.

Figure 25. Basic structure of a five-volt tolerant I/O port bit

is a potential specific to five-volt tolerant I/Os and different from V

Table 35. Port bit configuration table

OSPEEDR(i)
OTYPER(i)
0
0
0
0
SPEED
[B:A]
1
1
1
1
DocID018909 Rev 11
PUPDR(i)
[B:A] [1:0]
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Table 39 gives the possible
.
DD
(1)
I/O configuration
GP output PP
GP output PP + PU
GP output PP + PD
Reserved
GP output OD
GP output OD + PU
GP output OD + PD
Reserved (GP output OD)
RM0090