Table 57. Supported Color Mode In Output; Table 58. Data Order In Memory; Dma2D Output Fifo - STMicroelectronics STM32F405 Reference Manual

Chrom-Art Accelerator™ controller (DMA2D)
000
001
010
011
100
11.3.8

DMA2D output FIFO

The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
• DMA2D output memory address register (DMA2D_OMAR)
•
DMA2D output offset register (DMA2D_OOR)
• DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in
Color Mode
ARGB8888
RGB888
RGB565
ARGB1555
ARGB4444
The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
11.3.9 DMA2D AHB master port timer
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
348/1731

Table 57. Supported color mode in output

CM[2:0]

Table 58. Data order in memory

@ + 3
A [7:0]
0
B [7:0]
1
G [7:0]
2
R [7:0]
3
R [4:0]G [5:3]
1 1
A [0]R [4:0]G [4:3]
1 1 1
A [3:0]R [3:0]
1 1
DocID018909 Rev 11
@ + 2
R [7:0]
0
R [7:0]
0
B [7:0]
2
G [7:0]
3
G [2:0]B [4:0] R
1 1 0
G [2:0]B [4:0] A [0]R
1 1 0
G [3:0]B [3:0] A
1 1 0
Color mode
ARGB8888
RGB888
RGB565
ARGB1555
ARGB4444
Table 58: Data order in memory
@ + 1 @ + 0
G [7:0] B
0
G [7:0] B
0
R [7:0] G
1
B [7:0] R
3
[4:0]G [5:3] G [2:0]B
0 0
[4:0]G [4:3] G [2:0]B
0 0 0
[3:0]R [3:0] G [3:0]B
0 0
RM0090
[7:0]
0
[7:0]
0
[7:0]
1
[7:0]
2
[4:0]
0
[4:0]
0
[3:0]
0