Embedded Sram; Flash Memory Overview; Bit Banding - STMicroelectronics STM32F405 Reference Manual

Memory and bus architecture
2.3.1

Embedded SRAM

The STM32F405xx/07xx and STM32F415xx/17xx feature 4 Kbytes of backup SRAM (see
Section 5.1.2: Battery backup
The STM32F42xxx and STM32F43xxx feature 4 Kbytes of backup SRAM (see
Section 5.1.2: Battery backup
The embedded SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits).
Read and write operations are performed at CPU speed with 0 wait state. The embedded
SRAM is divided into up to three blocks:
•
SRAM1 and SRAM2 mapped at address 0x2000 0000 and accessible by all AHB
masters.
•
SRAM3 (available on STM32F42xxx and STM32F43xxx) mapped at address
0x2002 0000 and accessible by all AHB masters.
• CCM (core coupled memory) mapped at address 0x1000 0000 and accessible only by
the CPU through the D-bus.
The AHB masters support concurrent SRAM accesses (from the Ethernet or the USB OTG
HS): for instance, the Ethernet MAC can read/write from/to SRAM2 while the CPU is
reading/writing from/to SRAM1 or SRAM3.
The CPU can access the SRAM1, SRAM2, and SRAM3 through the System Bus or through
the I-Code/D-Code buses when boot from SRAM is selected or when physical remap is
selected
SYSCFG controller). To get the max performance on SRAM execution, physical remap
should be selected (boot or software selection).
2.3.2

Flash memory overview

The Flash memory interface manages CPU AHB I-Code and D-Code accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms. It accelerates code execution with a system of instruction
prefetch and cache lines.
The Flash memory is organized as follows:
•
A main memory block divided into sectors.
•
System memory from which the device boots in System memory boot mode
•
512 OTP (one-time programmable) bytes for user data.
•
Option bytes to configure read and write protection, BOR level, watchdog
software/hardware and reset when the device is in Standby or Stop mode.
Refer to
2.3.3

Bit banding

The Cortex
each word in an alias region of memory to a bit in a bit-band region of memory. Writing to a
word in the alias region has the same effect as a read-modify-write operation on the
targeted bit in the bit-band region.
In the STM32F4xx devices both the peripheral registers and the SRAM are mapped to a bit-
band region, so that single bit-band write and read operations are allowed. The operations
68/1731
(Section 9.2.1: SYSCFG memory remap register (SYSCFG_MEMRMP)
Section 3: Embedded Flash memory interface
®
-M4 with FPU memory map includes two bit-band regions. These regions map
DocID018909 Rev 11
domain) plus 192 Kbytes of system SRAM.
domain) plus 256 Kbytes of system SRAM.
for more details.
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in the