Figure 307. Usart Example Of Synchronous Transmission; Figure 308. Usart Data Clock Timing Diagram (M=0) - STMicroelectronics STM32F405 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
has been written). This means that it is not possible to receive a synchronous data without
transmitting data.
The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These
bits should not be changed while the transmitter or the receiver is enabled.
It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
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Figure 307. USART example of synchronous transmission

USART

Figure 308. USART data clock timing diagram (M=0)

Idle or preceding
Start
transmission
Data on TX
(from master)
Start
Data on RX
(from slave)
Capture Strobe
DocID018909 Rev 11
RX
Data out
TX
Data in
Synchronous device
(e.g. slave SPI)
SCLK
Clock
M=0 (8 data bits)
0 1 2 3 4
LSB
0 1 2 3 4
LSB
Idle or next
Stop transmission
*
*
*
*
5 6 7
MSB Stop
5 6 7
MSB
*
* LBCL bit controls last data clock pulse
RM0090