Table 310. Document Revision History - STMicroelectronics STM32F405 Reference Manual

Revision history
40 Revision history
Date
15-Sep-2011
19-Oct-2012
19-Oct-2012
1704/1731

Table 310. Document revision history

Version
1 Initial release.
Updated reference documents and added
products on cover page.
MEMORY:
Updated Section 2: Memory and bus
PWR:
Updated VDDA and VREF+ decoupling capacitor in
supply overview.
Updated case of no external battery in
domain.
VOSRDY bit changed to read-only in
2
control/status register
Removed VDDA in
(PVD) and remove VDDA in PVDO bit description
PWR power control/status register
RCC:
Updated Figure 20: Simplified diagram of the reset circuit
minimum reset pulse duration guaranteed by pulse generator
restricted to internal reset sources.
GPIOs:
Updated Section 8.3.1: General-purpose I/O
DMA:
Updated direct mode description in
features.
Updated direct mode description in
mode, and
Updated register access in
Modified Stream2 /Channel 2 in
2
Added note related to EN bit in
(continued)
configuration register (DMA_SxCR) (x =
NDT[15:0] bits in
register (DMA_SxNDTR) (x =
Interrupts:
Updated number of maskable interrupts to 82 in
NVIC featuress.
Updated Section 12.2: External interrupt/event controller
DocID018909 Rev 11
Changes
(PWR_CSR).
Section 5.2.3: Programmable voltage detector
(PWR_CSR)).
Section 10.3.12: FIFO/: Direct
Section 10.5: DMA
Table 42: DMA1 request
Section 10.5.5: DMA stream x
Section 10.5.6: DMA stream x number of data
0..7).
Table 1: Applicable
architecture.
Figure 7: Power
Section 5.1.2: Battery backup
Section 5.4.3: PWR power
(Section 5.4.3:
and
(GPIO).
Section 10.2: DMA main
Section : Memory-to-peripheral
mode.
registers.
mapping.
0..7). Updated definition of
Section 12.1.1:
(EXTI).
RM0090