Table 11. Number Of Wait States According To Cpu Clock (Hclk) Frequency (Stm32F42Xxx And Stm32F43Xxx) - STMicroelectronics STM32F405 Reference Manual

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Table 11. Number of wait states according to CPU clock (HCLK) frequency
Wait states (WS)
(LATENCY)
0 WS (1 CPU cycle)
1 WS (2 CPU cycles)
2 WS (3 CPU cycles)
3 WS (4 CPU cycles)
4 WS (5 CPU cycles)
5 WS (6 CPU cycles)
6 WS (7 CPU cycles)
7 WS (8 CPU cycles)
8 WS (9 CPU cycles)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states needed to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
1. Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency
1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4. Program the new number of wait states to the LATENCY bits in FLASH_ACR
5. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register
(STM32F42xxx and STM32F43xxx)
Voltage range
2.7 V - 3.6 V
0 <HCLK≤ 30
30 <HCLK ≤ 60
60 <HCLK ≤ 90
90 <HCLK ≤ 120
120 <HCLK ≤ 150 96 < HCLK≤ 120
150 <HCLK ≤ 180 120 <HCLK ≤ 144
144 <HCLK ≤ 168
168 <HCLK ≤ 180
DocID018909 Rev 11
Embedded Flash memory interface
HCLK (MHz)
Voltage range Voltage range
2.4 V - 2.7 V
0 <HCLK ≤ 24 0 <HCLK ≤ 22
24 < HCLK≤ 48 22 <HCLK ≤ 44
48 < HCLK≤ 72 44 < HCLK≤ 66
66 <HCLK ≤ 88
72 < HCLK≤ 96
88 < HCLK≤ 110
110 < HCLK≤ 132
132 < HCLK≤ 154
154 <HCLK ≤ 176
176 <HCLK ≤ 180
Voltage range
1.8 V - 2.1 V
2.1 V - 2.4 V
Prefetch OFF
0 < HCLK ≤ 20
20 <HCLK ≤ 40
40 < HCLK≤ 60
60 < HCLK≤ 80
80 < HCLK≤ 100
100 < HCLK≤ 120
120 < HCLK≤ 140
140 < HCLK≤ 160
160 < HCLK≤ 168
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