Rtc Timestamp Sub Second Register (Rtc_Tsssr) - STMicroelectronics STM32F405 Reference Manual

Real-time clock (RTC)
26.6.15

RTC timestamp sub second register (RTC_TSSSR)

Address offset: 0x38
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
r r r
15 14 13
r r r
Bits 31:16 Reserved
Bits 15:0 SS: Sub second value
SS[15:0] is the value of the synchronous prescaler's counter when the timestamp event
occurred.
Note: The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
26.6.16 RTC calibration register (RTC_CALR)
Address offset: 0x3C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
r r r
15 14 13
CALP CALW8 CALW16
rw rw rw
820/1731
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
Reserved
r r r r
DocID018909 Rev 11
24 23 22 21
Reserved
r r r r
8 7 6 5
SS[15:0]
r r r r
24 23 22 21
Reserved
r r r r
8 7 6 5
rw rw rw rw
20 19 18
r r r
4 3 2
r r r
20 19 18
r r r
4 3 2
CALM[8:0]
rw rw rw
RM0090
17 16
r r
1 0
r r
17 16
r r
1 0
rw rw