Table 36. Flexible Swj-Dp Pin Assignment - STMicroelectronics STM32F405 Reference Manual

RM0090
Full SWJ (JTAG-DP + SW-DP) - Reset state
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
JTAG-DP Disabled and SW-DP Enabled
JTAG-DP Disabled and SW-DP Disabled
•
GPIO
Configure the desired I/O as output or input in the GPIOx_MODER register.
•
Peripheral alternate function
For the ADC and DAC, configure the desired I/O as analog in the GPIOx_MODER
register.
For other peripherals:
–
–
–
•
EVENTOUT
Configure the I/O pin used to output the Cortex
connecting it to AF15
Note: EVENTOUT is not mapped onto the following I/O pins: PC13, PC14, PC15, PH0, PH1 and
PI8.
Please refer to the "Alternate function mapping" table in the datasheets for the detailed
mapping of the system and peripherals' alternate function I/O pins.

Table 36. Flexible SWJ-DP pin assignment

Available debug ports
Configure the desired I/O as an alternate function in the GPIOx_MODER register
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDR registers, respectively
Connect the I/O to the desired AFx in the GPIOx_AFRL or GPIOx_AFRH register
DocID018909 Rev 11
General-purpose I/Os (GPIO)
SWJ I/O pin assigned
PA13 / PA14 /
PA15 /
JTMS/ JTCK/
JTDI
SWDIO SWCLK
X X X
X X X
X X
®
-M4 with FPU EVENTOUT signal by
PB3 / PB4/
JTDO NJTRST
X X
X
Released
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