Figure 410. Usb Otg Interface Block Diagram; High-Speed Otg Phy - STMicroelectronics STM32F405 Reference Manual

USB on-the-go high-speed (OTG_HS)
1. The USB DMA cannot directly address the internal Flash memory.
35.3.1

High-speed OTG PHY

The USB OTG HS core embeds an ULPI interface to connect an external HS phy.
35.3.2 External Full-speed OTG PHY using the I2C interface
The USB OTG HS core embeds an I
35.3.3 Embedded Full-speed OTG PHY
The full-speed OTG PHY includes the following components:
•
FS/LS transceiver module used by both host and Device. It directly drives transmission
and reception on the single-ended USB lines.
• Integrated ID pull-up resistor used to sample the ID line for A/B Device identification.
•
DP/DM integrated pull-up and pull-down resistors controlled by the OTG_HS core
depending on the current role of the device. As a peripheral, it enables the DP pull-up
resistor to signal full-speed peripheral connections as soon as V
a valid level (B-session valid). In host mode, pull-down resistors are enabled on both
DP/DM. Pull-up and pull-down resistors are dynamically switched when the peripheral
role is changed via the host negotiation protocol (HNP).
• Pull-up/pull-down resistor ECN circuit
The DP pull-up consists of 2 resistors controlled separately from the OTG_HS as per
the resistor Engineering Change Notice applied to USB Rev2.0. The dynamic trimming
1372/1731

Figure 410. USB OTG interface block diagram

2
C interface allowing to connect an external FS phy.
DocID018909 Rev 11
RM0090
is sensed to be at
BUS