Table 221. Fsmc_Bcrx Bit Fields; Figure 435. Mode1 Write Accesses - STMicroelectronics STM32F405 Reference Manual

RM0090
The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this one HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4

Figure 435. Mode1 write accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]

Table 221. FSMC_BCRx bit fields

Bit name
Reserved
CBURSTRW
CPSIZE
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID
DocID018909 Rev 11
Flexible static memory controller (FSMC)
Memory transaction
ADDSET
HCLK cycles
0x000
0x0 (no effect on asynchronous mode)
0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
0.
0x0
0x0 (no effect on asynchronous mode)
As needed
Don't care
0x0
Meaningful only if bit 15 is 1
0x0
0x1
Don't care
As needed
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
Value to set
ai15558
1541/1731
1588