Interrupt Mask Register (Exti_Imr) - STMicroelectronics STM32F405 Reference Manual

Interrupts and events
12.3 registers
EXTI
Refer to
register descriptions.
12.3.1

Interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
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Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Interrupt mask on line x
12.3.2 Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31 30 29
15 14 13
MR15 MR14 MR13 MR12
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Bits 31:23 Reserved, must be kept at reset value.
Bits 22:0 MRx: Event mask on line x
386/1731
Section 1.1: List of abbreviations for registers
28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
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0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
28 27 26 25
Reserved
12 11 10 9
MR11 MR10 MR9
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0: Event request from line x is masked
1: Event request from line x is not masked
DocID018909 Rev 11
for a list of abbreviations used in
24 23 22 21
MR22 MR21
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8 7 6 5
MR8 MR7 MR6 MR5
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24 23 22 21
MR22 MR21
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8 7 6 5
MR8 MR7 MR6 MR5
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20 19 18 17
MR20 MR19 MR18 MR17
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4 3 2 1
MR4 MR3 MR2 MR1
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20 19 18 17
MR20 MR19 MR18 MR17
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4 3 2 1
MR4 MR3 MR2 MR1
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RM0090
16
MR16
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0
MR0
rw
16
MR16
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0
MR0
rw