Figure 114. Output Stage Of Capture/Compare Channel (Channel 1 To 3); Figure 115. Output Stage Of Capture/Compare Channel (Channel 4); Input Capture Mode - STMicroelectronics STM32F405 Reference Manual

Advanced-control timers (TIM1&TIM8)
ETR
CNT>CCR1
CNT=CCR1
ETR
CNT > CCR4
CNT = CCR4
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
17.3.6

Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to '0' or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when you write it to '0'.
530/1731

Figure 114. Output stage of capture/compare channel (channel 1 to 3)

OC1REF
Output mode
controller
OC1CE OC1M[2:0]
TIM1_CCMR1

Figure 115. Output stage of capture/compare channel (channel 4)

OC4 REF
Output mode
controller
OC2M[2:0]
TIM1_CCMR2
DocID018909 Rev 11
To the master mode
controller
'0'
x0
01
OC1_DT
11
Dead-time
generator
OC1N_DT
11
10
'0'
0x
DTG[7:0] CC1NE CC1E
TIM1_BDTR TIM1_CCER
To the master mode
controller
0
Output
enable
1 circuit
CC1P
TIM1_CCER
0
Output
enable
circuit
1
CC1NE CC1E TIM1_CCER
MOE OSSI OSSR
CC1NP
TIM1_CCER
0
Output
enable
circuit
1
CC4P
TIM1_CCER
CC4E TIM1_CCER
MOE OSSI TIM1_BDTR
TIM1_CR2
OIS4
RM0090
OC1
OC1N
TIM1_BDTR
OC4