Adc Watchdog Lower Threshold Register (Adc_Ltr) - STMicroelectronics STM32F405 Reference Manual

RM0090
13.13.8

ADC watchdog lower threshold register (ADC_LTR)

Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
13.13.9 ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29
15 14 13
SQ16_0 SQ15[4:0]
rw rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
27 26 25
11 10 9
rw rw rw
These bits are written by software to define the lower threshold for the analog watchdog.
28 27 26 25
Reserved
12 11 10 9
rw rw rw rw
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
These bits are written by software with the channel number (0..18) assigned as the 16th in
the conversion sequence.
DocID018909 Rev 11
Analog-to-digital converter (ADC)
24 23 22 21
Reserved
8 7 6 5
LT[11:0]
rw rw rw rw
24 23 22 21
L[3:0]
rw rw rw
8 7 6 5
SQ14[4:0]
rw
20 19 18 17
4 3 2 1
rw rw rw rw
20 19 18 17
SQ16[4:1]
rw rw rw rw
4 3 2 1
SQ13[4:0]
rw rw rw rw
16
0
rw
16
rw
0
rw
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