RM0090
30.5
USART mode configuration
Asynchronous mode
Hardware flow control
Multibuffer communication (DMA)
Multiprocessor communication
Synchronous
Smartcard
Half-duplex (single-wire mode)
IrDA
LIN
1. X = supported; NA = not applicable.
30.6
USART registers
Refer to Section: List of abbreviations for registers for a list of abbreviations used in register
descriptions.
The peripheral registers have to be accessed by half-words (16 bits) or words (32 bits).
30.6.1
Status register (USART_SR)
Address offset: 0x00
Reset value: 0x00C0 0000
31
30
29
15
14
13
Reserved
Universal synchronous asynchronous receiver transmitter (USART)
Table 147. USART mode configuration
USART modes
28
27
26
25
12
11
10
9
CTS
rc_w0
DocID018909 Rev 11
USART
USART
USART
1
2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
24
23
22
21
Reserved
8
7
6
5
LBD
TXE
TC
RXNE
rc_w0
r
rc_w0
rc_w0
(1)
UART4
UART5
3
X
X
NA
NA
X
X
X
X
NA
NA
NA
NA
X
X
X
X
X
X
20
19
18
4
3
2
IDLE
ORE
NF
r
r
r
USART
6
X
X
X
X
X
X
X
X
X
17
16
1
0
FE
PE
r
r
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