Figure 443. Mode D Read Accesses; Figure 444. Mode D Write Accesses - STMicroelectronics STM32F405 Reference Manual

RM0090
Mode D - asynchronous access with extended address

Figure 443. Mode D read accesses

A[25:0]
NADV
NEx
NOE
NWE
High
D[15:0]
ADDSET
HCLK cycles

Figure 444. Mode D write accesses

A[25:0]
NADV
NEx
NOE
NWE
D[15:0]
ADDSET
HCLK cycles
DocID018909 Rev 11
Flexible static memory controller (FSMC)
Memory transaction
data driven
by memory
DATAST
HCLK cycles
ADDHLD
HCLK cycles
Memory transaction
1HCLK
data driven by FSMC
(DATAST+ 1)
HCLK cycles
ADDHLD
HCLK cycles
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