Figure 107. Control Circuit In Normal Mode, Internal Clock Divided By 1; Figure 108. Ti2 External Clock Connection Example; Clock Selection - STMicroelectronics STM32F405 Reference Manual

Advanced-control timers (TIM1&TIM8)
17.3.4

Clock selection

The counter clock can be provided by the following clock sources:
•
Internal clock (CK_INT)
•
External clock mode1: external input pin
•
External clock mode2: external trigger input ETR
•
Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
one timer as prescaler for another timer
Internal clock source (CK_INT)
If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIMx_CR1
register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 107
without prescaler.

Figure 107. Control circuit in normal mode, internal clock divided by 1

External clock source mode 1
This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.
526/1731
shows the behavior of the control circuit and the upcounter in normal mode,
Internal clock
CEN=CNT_EN
CNT_INIT
Counter clock = CK_CNT = CK_PSC
Counter register

Figure 108. TI2 external clock connection example

TI2F_Rising
Edge
TI2
Filter
Detector
TI2F_Falling
ICF[3:0]
TIMx_CCMR1
DocID018909 Rev 11
for more details.
UG
31 32 33 34 35 36
TIMx_SMCR
TS[2:0]
TI2F
or
TI1F
ITRx
0xx
TI1_ED
100
TI1FP1
101
0
TI2FP2
110
ETRF
1
111
CC2P
CK_INT
TIMx_CCER
(internal clock)
00 01 02 03 04 05 06 07
or
or
encoder
mode
external clock
TRGI
mode 1
CK_PSC
ETRF external clock
mode 2
internal clock
mode
ECE SMS[2:0]
TIMx_SMCR
RM0090
Using