Figure 341. Receive Fifo States; Time Triggered Communication Mode - STMicroelectronics STM32F405 Reference Manual

RM0090
32.7.2

Time triggered communication mode

In this mode, the internal counter of the CAN hardware is activated and used to generate the
Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx
and Tx mailboxes). The internal counter is incremented each CAN bit time (refer to
Section 32.7.7: Bit
Of Frame bit in both reception and transmission.
32.7.3 Reception handling
For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.
Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see
timing). The internal counter is captured on the sample point of the Start

Figure 341. Receive FIFO states

EMPTY
Valid Message
FMP=0x00
FOVR=0
Received
Release
Mailbox
DocID018909 Rev 11
Section 32.7.4: Identifier
PENDING_1
FMP=0x01
FOVR=0
Valid Message
Release
Received
Mailbox
RFOM=1
PENDING_2
FMP=0x10
FOVR=0
Valid Message
Release
Mailbox Received
RFOM=1
PENDING_3
Valid Message
FMP=0x11
FOVR=0
Release
Mailbox
RFOM=1
Controller area network (bxCAN)
filtering.
Received
OVERRUN
FMP=0x11
FOVR=1
Valid Message
Received
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