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RM0090
37.6.2
NAND Flash / PC Card supported memories and transactions
Table 288
allowed (or not supported) by the NAND Flash / PC Card controller are shown in gray.
Device
NAND 8-bit
NAND 16-bit
37.6.3
Timing diagrams for NAND Flash memory and PC Card
Each PC Card/CompactFlash and NAND Flash memory bank is managed through a set of
registers:
•
Control register: FMC_PCRx
•
Interrupt status register: FMC_SRx
•
ECC register: FMC_ECCRx
•
Timing register for Common memory space: FMC_PMEMx
•
Timing register for Attribute memory space: FMC_PATTx
•
Timing register for I/O space: FMC_PIOx
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any PC Card/CompactFlash or NAND Flash access,
plus one parameter that defines the timing for starting driving the data bus when a write
access is performed.
memory accesses, knowing that Attribute and I/O (only for PC Card) memory space access
timings are similar.
shows the supported devices, access modes and transactions. Transactions not
Table 288. Supported memories and transactions
Mode
R/W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Asynchronous R
Asynchronous W
Figure 474
DocID018909 Rev 11
AHB
Memory
data size
data size
not allowed
8
8
Y
8
8
Y
16
8
Y
16
8
Y
32
8
Y
32
8
Y
8
16
Y
8
16
N
16
16
Y
16
16
Y
32
16
Y
32
16
Y
shows the timing parameter definitions for common
Flexible memory controller (FMC)
Allowed/
Comments
-
-
Split into 2 FMC accesses
Split into 2 FMC accesses
Split into 4 FMC accesses
Split into 4 FMC accesses
-
-
-
-
Split into 2 FMC accesses
Split into 2 FMC accesses
1637/1731
1669
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