Configuration Register (Wwdg_Cfr) - STMicroelectronics STM32F405 Reference Manual

RM0090
22.6.2

Configuration register (WWDG_CFR)

Address offset: 0x04
Reset value: 0x0000 007F
31 30 29 28
15 14 13 12
Reserved
Bit 31:10 Reserved, must be kept at reset value.
Bit 9 EWI: Early wakeup interrupt
Bits 8:7 WDGTB[1:0]: Timer base
Bits 6:0 W[6:0]: 7-bit window value
22.6.3 Status register (WWDG_SR)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 EWIF: Early wakeup interrupt flag
27 26 25
11 10 9
EWI
rs
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK1 div 4096) div 1
01: CK Counter Clock (PCLK1 div 4096) div 2
10: CK Counter Clock (PCLK1 div 4096) div 4
11: CK Counter Clock (PCLK1 div 4096) div 8
These bits contain the window value to be compared to the downcounter.
27 26 25
11 10 9
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing '0'. A write of '1' has no effect. This bit is also set if the interrupt is not
enabled.
DocID018909 Rev 11
24 23 22
Reserved
8 7 6
WDGTB[1:0]
rw
24 23 22
Reserved
8 7 6
Reserved
Window watchdog (WWDG)
21 20 19 18
5 4 3 2
W[6:0]
rw
21 20 19 18
5 4 3 2
17 16
1 0
17 16
1 0
EWIF
rc_w0
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