Figure 436. Modea Read Accesses; Figure 437. Modea Write Accesses - STMicroelectronics STM32F405 Reference Manual

RM0090
Mode A - SRAM/PSRAM (CRAM) OE toggling
1. NBL[1:0] are driven low during read access.

Figure 436. ModeA read accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
High
D[15:0]

Figure 437. ModeA write accesses

A[25:0]
NBL[1:0]
NEx
NOE
NWE
D[15:0]
DocID018909 Rev 11
Flexible static memory controller (FSMC)
Memory transaction
ADDSET DATAST
HCLK cycles HCLK cycles
Memory transaction
ADDSET
HCLK cycles
data driven
by memory
1HCLK
data driven by FSMC
(DATAST + 1)
HCLK cycles
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