Table 186. Clock Range; Figure 353. Mdio Timing And Frame Structure - Read Cycle; Media-Independent Interface: Mii - STMicroelectronics STM32F405 Reference Manual

Ethernet (ETH): media access control (MAC) with DMA controller
MDC
MDIO
SMI clock selection
The MAC initiates the Management Write/Read operation. The SMI clock is a divided clock
whose source is the application clock (AHB clock). The divide factor depends on the clock
range setting in the MII Address register.
Table 186
33.4.2

Media-independent interface: MII

The media-independent interface (MII) defines the interconnection between the MAC
sublayer and the PHY for data transfer at 10 Mbit/s and 100 Mbit/s.
1120/1731

Figure 353. MDIO timing and frame structure - Read cycle

32 1's 0 1 1 0
Start
OP
Preamble
of
code
frame
Data to PHY
shows how to set the clock ranges.
Selection
000
001
010
011
100
101, 110, 111
DocID018909 Rev 11
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
Register address Turn
PHY address

Table 186. Clock range

HCLK clock
60-100 MHz
100-150 MHz
20-35 MHz
35-60 MHz
150-180 MHz
Reserved
D15 D14 D1 D0
data
around
Data from PHY
MDC clock
AHB clock / 42
AHB clock / 62
AHB clock / 16
AHB clock / 26
AHB clock / 102
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RM0090
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