Table 223. Fsmc_Bcrx Bit Fields; Table 224. Fsmc_Btrx Bit Fields - STMicroelectronics STM32F405 Reference Manual

Flexible static memory controller (FSMC)
The differences compared with mode1 are the toggling of NOE and the independent read
and write timings.
Bit
number
31-20
19
18:16
15
14
13
12
11
10
9
8
7
6
5-4
3-2
1
0
Bit
number
31:30
29-28
27-24
23-20
19-16
15-8
7-4
3-0
1544/1731

Table 223. FSMC_BCRx bit fields

Bit name
Reserved 0x000
CBURSTRW 0x0 (no effect on asynchronous mode)
CPSIZE 0x0 (no effect on asynchronous mode)
Set to 1 if the memory supports this feature. Otherwise keep at
ASYNCWAIT
0.
EXTMOD 0x1
WAITEN 0x0 (no effect on asynchronous mode)
WREN As needed
WAITCFG Don't care
WRAPMOD 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
MTYP[0:1] As needed, exclude 0x2 (NOR Flash)
MUXEN 0x0
MBKEN 0x1

Table 224. FSMC_BTRx bit fields

Bit name
Reserved 0x0
ACCMOD 0x0
DATLAT Don't care
CLKDIV Don't care
BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
Duration of the second access phase (DATAST HCLK cycles) for
DATAST
read accesses.
ADDHLD Don't care
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
ADDSET[3:0]
Minimum value for ADDSET is 0.
DocID018909 Rev 11
Value to set
Value to set
RM0090