Figure 39. Fifo Structure - STMicroelectronics STM32F405 Reference Manual

Advanced arm-based 32-bit mcus

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FIFO structure

The FIFO is used to temporarily store data coming from the source before transmitting them

to the destination.

Each stream has an independent 4-word FIFO and the threshold level is software-

configurable between 1/4, 1/2, 3/4 or full.

To enable the use of the FIFO threshold level, the direct mode must be disabled by setting

the DMDIS bit in the DMA_SxFCR register.

The structure of the FIFO differs depending on the source and destination data widths, and

is described in

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

FIFO threshold and burst configuration

Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR

content pointed by the FIFO threshold must exactly match to an integer number of memory

burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or

DMA_LISR register) will be generated when the stream is enabled, then the stream will be

automatically disabled. The allowed and forbidden configurations are described in the

Figure 39: FIFO

Figure 39. FIFO structure

Source: byte

Source: byte

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

Source: half-word

H7 H6 H5 H4 H3 H2 H1 H0

DocID018909 Rev 11

DMA controller (DMA)

Destination: word

W3, W2, W1, W0

Destination: half-word

H7, H6, H5, H4, H3, H2, H1, H0

Destination: word

W3, W2, W1, W0

Destination: byte

B15 B14 B13 B12 B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

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Figure 39. Fifo Structure - STMicroelectronics STM32F405 Reference Manual

Figure 39. FIFO structure

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