Dma Stream X Peripheral Address Register (Dma_Sxpar) (X = 0..7) - STMicroelectronics STM32F405 Reference Manual

DMA controller (DMA)
10.5.7

DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)

Address offset: 0x18 + 0x18 × stream number
Reset value: 0x0000 0000
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Bits 31:0 PAR[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
10.5.8 DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
Address offset: 0x1C + 0x18 × stream number
Reset value: 0x0000 0000
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Bits 31:0 M0A[31:0]: Memory 0 address
10.5.9 DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
Address offset: 0x20 + 0x18 × stream number
Reset value: 0x0000 0000
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334/1731
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Base address of Memory area 0 from/to which the data will be read/written.
These bits are write-protected. They can be written only if:
– the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
– the stream is enabled (EN='1' in DMA_SxCR register) and bit CT = '1' in the
DMA_SxCR register (in Double buffer mode).
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DocID018909 Rev 11
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PAR[31:16]
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8 7 6 5
PAR[15:0]
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M0A[31:16]
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8 7 6 5
M0A[15:0]
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M1A[31:16]
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8 7 6 5
M1A[15:0]
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20 19 18 17
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4 3 2 1
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4 3 2 1
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RM0090
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