Figure 227. Aes-Ctr Mode Decryption; Figure 228. Initial Counter Block Structure For The Counter Mode - STMicroelectronics STM32F405 Reference Manual

RM0090
1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or
after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when
encoding); P: plain text; IV: Initialization vectors.
Figure 228
of three distinct fields.
•
Nonce is a 32-bit, single-use value. A new nonce should be assigned to each different
communication.
•
The initialization vector (IV) is a 64-bit value and the standard specifies that the
encryptor must choose IV so as to ensure that a given value is used only once for a
given key
•
The counter is a 32-bit big-endian integer that is incremented each time a block has
been encrypted. The initial value of the counter should be set to '1'.
The block increments the least significant 32 bits, while it leaves the other (most significant)
96 bits unchanged.

Figure 227. AES-CTR mode decryption

shows the structure of the IV block as defined by the standard [2]. It is composed

Figure 228. Initial counter block structure for the Counter mode

DocID018909 Rev 11
Cryptographic processor (CRYP)
725/1731
757