General Timing Rules - STMicroelectronics STM32F405 Reference Manual

Flexible memory controller (FMC)
37.5.3

General timing rules

Signals synchronization
• All controller output signals change on the rising edge of the internal clock (HCLK)
•
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
–
37.5.4 NOR Flash/PSRAM controller asynchronous transactions
Asynchronous static memories (NOR Flash, PSRAM, SRAM)
• Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
•
The FMC always samples the data before de-asserting the NOE signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
•
If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to
four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D
modes for read and write operations. For example, read operation can be performed in
mode A and write in mode B.
•
If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the
FMC can operate in Mode1 or Mode2 as follows:
–
–
1604/1731
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.
Mode 1 is the default mode when SRAM/PSRAM memory type is selected
(MTYP[1:0] = 0x0 or 0x01 in the FMC_BCRx register)
Mode 2 is the default mode when NOR memory type is selected
(MTYP[1:0] = 0x10 in the FMC_BCRx register).
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