Figure 208. Counter Timing Diagram, Internal Clock Divided By 4; Figure 209. Counter Timing Diagram, Internal Clock Divided By N; Preloaded) - STMicroelectronics STM32F405 Reference Manual

Basic timers (TIM6&TIM7)
Figure 210. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
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Figure 208. Counter timing diagram, internal clock divided by 4

CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)

Figure 209. Counter timing diagram, internal clock divided by N

CK_INT
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
Auto-reload register
Write a new value in TIMx_ARR
DocID018909 Rev 11
0035
0036
1F 20

preloaded)

31 32 33 34 35 36 00
FF
RM0090
0000 0001
00
01 02 03 04 05 06 07
36