Oversampling By 8; Oversampling By 16; Pclk = 16 Mhz Or F Pclk = 24 Mhz - STMicroelectronics STM32F405 Reference Manual

Universal synchronous asynchronous receiver transmitter (USART)
Table 134. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps
5 38.4 KBps
6 57.6 KBps
7 115.2 KBps
8 230.4 KBps
9 460.8 KBps
10 921.6 KBps
11 2 MBps
12 3 MBps
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.
Table 135. Error calculation for programmed baud rates at f
Baud rate
S.No Desired
1 1.2 KBps
2 2.4 KBps
3 9.6 KBps
4 19.2 KBps
5 38.4 KBps
6 57.6 KBps
974/1731

oversampling by 8

Oversampling by 8 (OVER8 = 1)
f = 8 MHz
PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 833.375
2.4 KBps 416.625
9.604 KBps 104.125
19.185 KBps 52.125
38.462 KBps 26
57.554 KBps 17.375
115.942 KBps 8.625
228.571 KBps 4.375
470.588 KBps 2.125
888.889 KBps 1.125
NA NA
NA NA

oversampling by 16

Oversampling by 16 (OVER8 = 0)
= 16 MHz
f PCLK
Value
programmed
Actual
in the baud
rate register
1.2 KBps 833.3125
2.4 KBps 416.6875
9.598 KBps 104.1875
19.208 KBps 52.0625
38.369 KBps 26.0625
57.554 KBps 17.375
DocID018909 Rev 11
= 8 MHz or f
PCLK
(1)
% Error =
(Calculated -
Desired)
Actual
B.rate /
Desired
B.rate
0 1.2 KBps
0.01 2.4 KBps
0.04 9.6 KBps
0.08 19.2 KBps
0.16 38.339 KBps
0.08 57.692 KBps
0.64 115.385 KBps
0.79 230.769 KBps
2.12 461.538 KBps
3.55 923.077 KBps
NA NA
NA NA
= 16 MHz or f
PCLK
(1)
% Error =
(Calculated -
Actual
Desired) B.rate /
Desired B.rate
0 1.2
0 2.4
0.02 9.6
0.04 19.2
0.08 38.4
0.08 57.554
RM0090
=12 MHz,
PCLK
f = 12 MHz
PCLK
Value
programmed
% Error
in the baud
rate register
1250
625
156.25
78.125
39.125 0.16
26 0.16
13 0.16
6.5 0.16
3.25 0.16
1.625 0.16
NA NA
NA NA
= 24 MHz,
PCLK
= 24 MHz
f PCLK
Value
programmed
% Error
in the baud
rate register
1250 0
625 0
156.25 0
78.125 0
39.0625 0
26.0625 0.08
0
0
0
0