Tim9/12 Slave Mode Control Register (Timx_Smcr) - STMicroelectronics STM32F405 Reference Manual

RM0090
19.4.2

TIM9/12 slave mode control register (TIMx_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 MSM: Master/Slave mode
12 11 10 9
Reserved
0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.
DocID018909 Rev 11
General-purpose timers (TIM9 to TIM14)
8 7 6 5
MSM TS[2:0]
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4 3 2 1
SMS[2:0]
Res.
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0
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